The present invention relates to a D/A (digital-to-analog) converter used in various electronic appliances and, more particularly, to a C-R type D/A converter which uses a capacitor array and a resistor string.
The type of circuit used for a D/A converter includes an R-2R ladder type circuit using a resistor network, a segment type circuit using a resistor string, a C-array type circuit using a capacitor array, a C-C type circuit prepared by coupling two sets of capacitor arrays, a C-R type circuit formed by combining together the C-array type circuit and R-segment type circuit, etc.
Where the R-2R ladder circuit is constituted by ion implantation resistors, the resistance value is varied due to the back gate effect with the result that the D/A conversion precision is decreased. Therefore, the R-2R ladder circuit has a drawback in that the number of bits capable of being converted is around 7 bits at most. Further, where the R-2R ladder circuit is formed with the use of impurity diffusion resistors or polysilicon resistors, the resistance value is small. Therefore, it is impossible to obtain a high conversion precision unless the resistance value of switch elements, controlled by digital input data, is made extremely small. However, it is technically difficult to make the resistance value of the switch elements extremely small. In this case as well, therefore, high conversion precision is not obtained.
In the segment type circuit using a resistor string or strings, resistor elements should be provided m=2.sup.n in number where the number of bits to be converted is "n". For this reason, when it is desired that a larger number of bits undergo a conversion operation, the area occupied by the resistor elements on a semiconductor chip becomes very large. This makes high integration impossible. Besides, the cost of the converter device increases.
Where the C-array type circuit is used to form a D/A converter, it is possible to increase the conversion precision because the capacitor is less dependent upon the voltage involved. In this case, however, the minimum capacitance value can not be made smaller than a specified value, and as the number of bits being treated increases, the capacitance value of upper bits, sequentially more weighted, increases accordingly. As a result, the area occupied by the capacitors on a semiconductor chip greatly increases, and the device cost rises.
Where the C-C type circuit is used for a D/A converter, it has the construction shown in FIG. 1. In FIG. 1, a capacitor C0 is a capacitor having a unit-capacitance C, and a capacitor Cc is a coupling capacitor. Capacitors C1L, C2L, . . . , ClL are used for conversion of lower bits, while capacitors C1H, C2H, . . . , CmH are used for conversion of upper bits. The capacitance values of the lower-bit capacitors C1L, C2L, . . . , ClL are C, 2C, . . . , C.sup.l-1 .multidot.C, respectively, while the capacitance values of the upper-bit capacitors C1H, C2H, . . . , CmH are C, 2C, . . . , 2.sup.m-1 .multidot.C, respectively. Switches S1, S2, . . . , Sl are connected correspondingly to the lower bit capacitors C1L, C2L, . . . , ClL, respectively. These switches are controlled by the lower bits V1, V2, . . . , Vl of a digital input data. Switches Sl+1, Sl+2, . . . , Sl+m are connected correspondingly to the upper bit capacitors C1H, C2H, . . . , CmH, respectively, and are controlled by the upper bits Vl+1, Vl+2, . . . , Vl+m of a digital input data, respectively. The switches S1, S2, . . . , Sl, Sl+1, Sl+2, . . . , Sl+m are controlled in accordance with the logic level of their corresponding input bit data V1, V2, . . . , Vl, Vl+1, Vl+2, . . . , Vl+m. More specifically, where the bit data has a logic level of "1", the switches are so controlled as to select a reference voltage Vref. Where the bit data has a logic level of "0", the switches are so controlled as to select a ground voltage GND. The lower and upper bit capacitors are thus respectively connected to the reference voltage Vref or the ground voltage GND.
When, with the above-mentioned construction, the total capacitance Ceff of the lower bit-capacitor array, as viewed from the coupling capacitor Cc, is set at a value equal to the unit-capacitance C of the capacitor C0, the output voltage Vout is expressed as follows. ##EQU1## Where Vk represents the logic level of "1", or "0", the symbol k representing 1, 2, . . . , l+m.
The D/A conversion characteristic expressed by the formula (1) is graphically shown in FIG. 2 as a linear characteristic curve.
In order that the total capacitance Ceff and the unit capacitance C, when set, may be equalized, however, the following conditional formula must be satisfied. Namely, ##EQU2## As seen in the formula (2), setting the total capacitor Ceff and the unit-capacitance C to equal value makes it necessary to set the capacitance value of the coupling capacitor Co to a value obtained by multiplying the unit-capacitance C by (2.sup.l /2.sup.l-1). That is to say, the capacitance value of the coupling capacitor Cc must be set at a value equal to a non-integral multiple of the unit-capacitance C of the capacitor array. However, a much higher manufacturing precision is required for setting such a non-integral multiple from the standpoint of manufacturing technique. Namely, it is difficult to achieve such high precision in the actual manufacturing process.
In the C-R type circuit, a C-array type circuit 11 and a segment type circuit 12, comprised of a resistor string, are combined together into a converter, as shown in FIG. 3. In this C-R type circuit, the resistor string comprised of resistor elements R1, R2, . . . , Rj, . . . , R.sub.M-2, R.sub.M-1, R.sub.M is connected between the reference voltage Vref and the ground voltage GND. Switches S1, . . . , Sj, . . . , S.sub.M-2, S.sub.M-1 are commonly connected at one end to an output node of Vstep voltage and connected at the other end to one end of their corresponding resistor elements R1, R2, . . . , R.sub.M-1, respectively. On the other hand, switches T1, T2, . . . , T.sub.N connect to any one of the reference voltage Vref, ground voltage GND and Vstep voltage output node ends of their corresponding capacitors C1, C2, . . . , C.sub.N (whose capacitance values are weighted in a binary manner so that those values may become sequentially greater from the capacitor C1 toward the capacitor C.sub.N), respectively, and the other ends being commonly connected to the output voltage terminal Vout. The capacitance value Ci is set such that Ci=2.sup.i-1 .multidot.C, where i represents 1, 2, . . . , l, . . . , N and C represents the unit-capacitance of the capacitors C1, . . . , C.sub.N. The switches S1, S.sub.M-1 and T1, . . . , T.sub.N are controlled, as indicated in FIG. 4, in accordance with the digital input bit data. Note here that, in FIG. 4, the numbers shown on the abscissa with respect to the switches S1 to S.sub.M-1 represent the switches turned on. That is to say, the switches S1, . . . , S.sub.M-1 are controlled in accordance with the logic levels of their corresponding lower bits of the digital input data, whereby any one of them is selectively turned on. On the other hand, the switches T1, T2, . . . , T.sub.N are controlled such that, as the upper bits of the digital input data increase in the bit location rank, they are sequentially turned on from the switch T1 toward T.sub.N. Further, a switch U1 is connected between an output terminal Vout of the C-array type circuit 11 and the ground voltage GND. The switch U1 is temporarily turned on in advance of the D/A conversion operation.
When it is assumed that the switch Sj of the switches S1, . . . , S.sub.M-1 (provided, however, that 1.ltoreq.j.ltoreq.M-1) has been turned on, then the voltage Vstep is expressed as follows. ##EQU3## When it is assumed that, at this time, the switches T1 to Tl-1 are connected to the reference voltage Vref; the switch Tl is connected to the Vstep output node; and the switches Tl+1 to T.sub.N are connected to the ground voltage GND, then the output voltage Vout is expressed as follows: ##EQU4## At this time, the capacitance value is C1=2.sup.i-1 .multidot.C (where C represents the unit-capacitance of the capacitor array C1, . . . , C.sub.N, i.e., the capacitance of the capacitor C1 and i=1, 2, . . . , l, . . . , N). Namely, the capacitors C1, . . . , C.sub.N are sequentially weighted in a bindary manner. Therefore, the above formula (4) is rewritten as follows. ##EQU5## By the way, ##EQU6## Therefore, ##EQU7##
The D/A conversion characteristic expressed by the above formula (7) has a non-linearity, as shown in FIG. 4.
The converter device having such a non-linear characteristic as shown in FIG. 4 has its use limited, for example, to use in a PCM coder or PCM decoder of a PCM (pulse code modulation) transmission terminal device. In the case of requiring the use of a linear characteristic, it is impossible to employ the C-R type circuit such as that shown in FIG. 3.